This invention relates to a method for switching Asynchronous Transfer Mode (hereinafter referred to as ATM) and an ATM switch used for multi-media.
Conventionally various types of ATM switches, for example, of a shared buffer switch type, an output buffer switch type or the like, have been suggested. In order to manage the traffic exhibiting strong burst with the ATM switches of the above-described type, a high speed/large capacity buffer has to be employed.
An ATM switch as shown in FIG. 7 has been proposed for managing the strong burst traffic not using such a high speed/large capacity buffer. Referring to FIG. 7, the conventional ATM switch comprises N input ports 101-1 to 101-N, low speed/large capacity RIRO (Random In Random Out) input buffers 102-1 to 102-N, each connected to the respective input ports 101-1 to 101-N, input buffer control sections 103-1 to 103-N for controlling the respective RIRO input buffers 102-1 to 102-N, N output ports 108-1 to 108-N, high speed/small capacity FIFO output buffers 106-1 to 106-N, each connected to the respective output ports 108-1 to 108-N, output buffer control sections 107-1 to 107-N for controlling the respective FIFO output buffers 106-1 to 106-N and outputting a back pressure signal 109 and a time division bus 105 for connecting the RIRO input buffers 102-1 to 102-N to the respective FIFO output buffers 106-1 to 106-N. The FIFO output buffers 106-1 to 106-N are allowed to receive N cells (N: the number of the input ports) simultaneously.
A cell input to the input port 101-1 is accumulated in a vacant space of the RIRO input buffer 102-1 through the input buffer control section 103-1. The input buffer control section 103-1 has N control queues 104-1 to 104-N for controlling cells accumulated in the RIRO input buffer 102-1 by each of the output ports 108-1 to 108-N. When the cell is accumulated in a vacant space of the RIRO input buffer 102-1, an accumulation address of the cell is stored in a control queue corresponding to an output port indicated by the output port information contained in the cell. The input buffer control section 103-1 refers to each of the control queues 104-1 to 104-N one after another to read out each cell based on the accumulation address prefixed thereto. The other input buffer control sections control in the same manner as described above.
Each cell read from the respective RIRO input buffers 102-1 to 102-N is stored in the FIFO output buffer corresponding to the output port indicated by the output port information contained in the cell via the time division bus 105.
When a vacant space of the FIFO output buffer 106-i becomes less than N cells, an output buffer control section 107-i for controlling write/read of the cell to/from the FIFO output buffer 106-i (1.ltoreq.i .ltoreq.N) outputs a back pressure signal 109 to all input buffer control sections 103-1 to 103-N so as to inhibit output of the cell addressed to the output port 108-i. When the back pressure signal 109 is received, the respective input buffer control sections 103-1 to 103-N sequentially output cells accumulated in the RIRO input buffers 102-1 to 102-N other than those cells addressed to the output port 108-i.
Utilizing a combination of the low speed/large capacity RIRO input buffers 102-1 to 102-N and high speed/small capacity FIFO output buffers 106-1 to 106-N to output a back pressure signal 109 from each of the FIFO output buffers 106-1 to 106-N allows for management of the strong burst traffic without using the high speed/large capacity buffer.
In order to realize a large scale ATM switch accommodating a large number of input ports and output ports using the aforementioned construction as shown in FIG. 7, it is necessary to utilize a large number of RIRO input buffers and FIFO output buffers. However a large number of those RIRO input buffers and FIFO output buffers may require increased interface interface with the time division bus, which is difficult to practically realize owing to the number of pins for connecting the RIRO input buffers and FIFO output buffers to the time division bus. Even though such ATM switch is realized, the resultant cost is substantially increased.
In order to decrease the number of interfaces with the time division bus, the construction shown in FIG. 8 has been proposed.
The ATM switch shown in FIG. 8 comprises NxK input ports 201-11 to 201-NK, N units of low speed/large capacity RIRO input multiplex buffers 202-1 to 202-N, input multiplex buffer control sections 203-1 to 203-N for controlling each write/read of cells to/from the RIRO input multiplex buffers 202-1 to 202-N, a time division bus 205, N units of high speed/small capacity FIFO output buffers 206-1 to 206-N, output buffer control sections 207-1 to 207-N for controlling read/write of cells from/to the FIFO output buffers 206-1 to 206-N, N units of low speed/large capacity RIRO output separation buffers 208-1 to 208-N and NxL units of output ports 209-11 to 209-NL. Each of the FIFO output buffers 206-1 to 206-N is able to receive N (the number of RIRO input multiplex buffers) cells simultaneously.
The RIRO input multiplex buffers 202-1 to 202-N have K input ports (201-11 to 201-1K) to (201-N1 to 201-NK) connected thereto, respectively. the RIRO output separation buffers 208-1 to 208-N have L output ports (209-11 to 209-1L) to (209-N1 to 209-NL) connected thereto, respectively.
A cell input to the input port 201-11 is accumulated in a vacant space of the RIRO input buffer 202-1 through the input multiplex buffer control section 203-1. The input multiplex buffer control section 203-1 has NXL control queues 204-11 to 204-NL for controlling cells accumulated in the RIRO input multiplex buffer 202-1 by each of the output ports 209-11 to 209-NL. When the cell is accumulated in the vacant space of the RIRO input multiplex buffer 202-1, an accumulation address of the cell is stored in a control queue corresponding to an output port indicated by the output port information contained in the cell. The input multiplex buffer control section 203-1 refers to the control queues 204-11 to 204-NL one after another so that each cell is read out based on the accumulation address prefixed to each of the control queues 204-11 to 204-NL. The rest of the input multiplex buffer control sections execute the same controlling.
Each cell multiplexed and read from the respective RIRO input multiplex buffers 202-1 to 202-N is stored in an FIFO output buffer corresponding to an output port indicated in the output port information contained by the cell via the time division bus 205.
Cells accumulated in the respective FIFO output buffers 206-1 to 206-N are read one by one and accumulated in a vacant space of the RIRO output separation buffers 208-1 to 208-N, respectively. The RIRO output separation buffers 208-1 to 208-N output the accumulated cell to an output port indicated by the output port information contained in the cell.
An output buffer control section 207-i for controlling write/read of cells to/from a FIFO output buffer 206-i (1.ltoreq.i&lt;N) outputs a back pressure signal 210 to all input multiplex buffer control sections 203-1 to 203-N when the vacant space of the KIRO buffer 206-i becomes less than N cells so as to inhibit output of cells addressed to the output ports 209-i1 to 209-iL connected to the FIFO output buffer 206-i, respectively.
In each input multiplex buffer control section 203-1 to 203-N, cells other than those addressed to the output ports 209-i to 209-i1 which have been accumulated in the RIRO input multiplex buffers 202-1 to 202-N are output sequentially.
The number of interface to the time division bus 205 can be decreased by connecting RIRO input multiplex buffers 202-1 to 202-N to FIFO output buffers 206-1 to 206-N, respectively via the time division bus 205 through multiplexing cells from a plurality of input ports.
With the conventional art shown in FIG. 8, when a large number of cells addressed to a certain output port are generated in the respective RIRO input buffers at a burst, the ratio of cells addressed to the certain output port which have been accumulated in the RIRO output separation buffer connected to the certain output port is increased. As a result, even though cells addressed to the other output port are accumulated in the RIRO input multiplex buffer, those cells cannot be output from the output port easily.
Furthermore in the conventional art shown in FIG. 8, each input multiplex buffer control section refers to each control queue by every output port sequentially so that each cell is read out based on the accumulation address prefixed to each of the control queues. So the same traffic amount is transferred from each of the RIRO input multiplex buffer to the certain output port.
Accordingly in case each of the RIRO input multiplex buffer has a different number of connections (active connection) for transferring cells existing between each RIRO input multiplex buffer and the certain output port, the same number of cells are transferred from the respective RIRO input multiplex buffer to the certain output port for a unit of time. In this conventional art shown in FIG. 8, each active connection addressed to the same output port uses different bandwidth, resulting in the failure to provide every user with equal service.